Carrier-based Sinusoidal Pulse Width Modulation Research Articles

Multilevel Inverter with Enhanced THD Value used in Grid Connected Applications

In this work, the relationships among pulse width modulation (PWM), sinusoidal pulse width modulation (SPWM), and space-vector pulse width modulation (SVPWM) for three-phase inverters will be analyzed to better comprehend their differences. detailed comparison of the three modulation schemes under study’s Total Harmonic Distortion (THD). High-power applications are increasingly concentrating on converter technology. This growing importance may be attributed to its improved output waveforms over the 3- carrier-based sinusoidal pulse width modulation (SPWM). To control and modulate multi-level inverters, many techniques are employed. These methods are categorized based on how frequently they switch. The ripple current rating, capacitance value, and voltage balance in the DC bus capacitors are all impacted by the pulse width modulation techniques. It is crucial to select the modulation method based on the current control requirements, as this determines the output voltage waveform’s harmonic content. SVPWM is gradually becoming more and more popular in industries because of its improved dc bus utilization and ease of digital realization. This work examines PWM, Sinusoidal, and SVPWM feeding a load connected to RL. Three different methodologies’ performances are compared as these methods are investigated through simulation with MATLAB/SIMULINK software.

A Generalized Switched-Capacitor Multilevel Inverter Topology with Voltage Boosting Ability and Reduced Inrush Current

This article presents a novel quadruple boost inverter (QBI) with an integrated boost stage that comprises an inductor, a capacitor, a switch, and an input source. The inductor on the input side limits the inrush current and also the capacitor charging current ripples. The QBI topology comprises a dc source, an input inductor, nine switches, three diodes, and capacitors. This produces a nine-level waveform, which reduces the need for additional filters such as inductors and capacitors. The proposed QBI is elementary, compact, and needs fewer components than existing nine levels inverter. Compared to the typical triangular carrier-based sinusoidal pulse width modulation, the newly developed parabolic level-shifted carrier has a much greater RMS value. Another advantage of the proposed topology is extension for generating higher voltage levels without increment in the blocking voltage across the switches. This makes the topology ideal for medium voltage high power applications. The output voltage has been determined in terms of selection, sizing, and expression. The proposed QBI is compared to existing similar nine-level inverters in order to assess its efficacy. The experiment is performed on a laboratory prototype to state the practical feasibility of QBI topology for the inductive load, variation in input, load, and modulation index.

Integrated Three-Level Dual-Phase Inverter

In view of reducing the number of inverter legs that provide dual-phase, three-level output voltages (as may be needed in an uninterruptible power supply), and that also provide a wide range of output frequencies (as needed in an advanced motor drive system with wide speed ranges), a three-level, dual-phase inverter topology is presented in this paper. Its three-level attribute was based on the F-type inverter topological concept, and its dual-output feature was based on the common representation of the inverter-leg concept. The proposed inverter could deliver single- and three-phase voltages to corresponding one- and three-phase loads, in common or different frequency modes of operation. A boundary between these modes of operation was established for the proposed inverter. An additional possibility of either operation in the one-phase or the three-phase system was offered by the inverter configuration. A modified carrier-based sinusoidal pulse-width modulation scheme is presented for the control of the inverter topology. The performances of the dual-phase inverter are given in the simulation results and demonstrated with a hardware prototype.

Evaluation of POD and APOD multicarrier SPWM techniques for three-phase seven-level diode clamped multilevel inverter fed induction motor drive using FPGA

Multilevel inverters have drawn tremendous interest in high power high voltage applications due to their merits such as reduced voltage stress on switches, lower EMI problems and reduction in THD. The MLI technology is also advantageous in improving output waveforms due to the higher number of levels in the waveform of output voltage along with a reduced input filter size which is useful for grid connected applications. This paper focuses on implementation of three-phase diode clamped multilevel inverter fed induction motor drive using various multicarrier-based sinusoidal pulse width modulation techniques. The performance analysis of the inverter is carried out using phase opposition disposition (POD) and alternate phase opposition disposition (APOD) techniques. In addition to this, the comparison of the modulation methods is also analysed. Simulation is performed using MATLAB/Simulink. The POD and APOD carrier-based sinusoidal pulse width modulation techniques for three-phase seven-level diode clamped multilevel inverter are implemented on VPE Spartan 3A DSP board using Xilinx field programmable gate array (FPGA) and the experimental results are presented to validate the effectiveness of the operation of the seven-level diode clamped multilevel inverter using PWM strategies.

Carrier-based sinusoidal pulse-width modulation techniques for flying capacitor modular multi-level cascaded converter

Carrier-based sinusoidal pulse-width modulation (PWM) techniques, such as phase disposoed PWM(PD-PWM) and phase shifted PWM (PS-PWM), are widely applied to control the modular multilevel cascaded converters (MMCC) having full H-bridge as sub-modules. This paper evaluates these PWM techniques when controlling a variant of the H-bridge MMCC, i.e. the MMCC five-level flying capacitor converter as sub-modules. This MMCC poses an extra challenge to PWM schemes; namely maintaining two inner floating capacitor voltage balancing. Two novel PWM techniques known as the swapped carrier PWM techniques are introduced for the control of this converter. The paper compares them with the two conventional ones using a performance metrics composed of voltage waveform performance, capability in natural flying capacitor voltage balancing, converter power loss, and switch utilisation. The results show that the proposed new PWM schemes outperform both conventional methods in both switching and conduction power losses and achieve similar performance like the PS-PWM under the three other metrics.

Simultaneous DC Current Balance and CMV Reduction for Parallel CSC System With Interleaved Carrier-Based SPWM

Parallel current source converter (CSC) has attracted increasing attention due to the potential advantages to increase the system power capacity, reliability, and output quality. Compared with multilevel space vector modulation (SVM) and selective harmonic elimination, carrier-based sinusoidal pulsewidth modulation (SPWM) enjoys inherent scalability and modularity, which is very easy to be implemented in N-CSC parallel system by interleaving the carriers. The dc current balance and common-mode voltage (CMV) are the main concerns in parallel CSC system and most of the research was focused on SVM. However, dc current balance and CMV reduction methods with interleaved SPWM were not well addressed. In this article, we mainly investigate three different interleaved SPWM methods, namely, bi-tri logic SPWM, six-step direct PWM, and direct duty-ratio PWM (DDPWM). The comparison results show that the proposed interleaved DDPWM can balance the dc current and suppress CMV simultaneously, which can improve the output quality and reduce load-side CMV stress effectively. The validity and effectiveness of the proposed methods are verified on a parallel CSC system with shared dc-link by simulation and experimental results.

A Sawtooth Carrier-Based PWM for Asymmetrical Six-Phase Inverters With Improved Common-Mode Voltage Performance

A sawtooth carrier-based sinusoidal pulse width modulation (SC-SPWM) technique for asymmetrical six-phase two-level inverters is proposed in this paper, which could reduce both the peak-to-peak amplitude and the changing frequency of the common-mode voltage (CMV). The intersection-plotting method reveals that the mirror symmetrical sawtooth carriers for two three-phase groups can help optimize the distribution of overlapping areas, which is the CMV reduction mechanism of SC-SPWM. Additionally, the Fourier analysis is employed to quantitatively evaluate the modulation index and harmonic performance of SC-SPWM compared with the conventional SPWM and two phase-shifted SPWM methods. Also, further analysis demonstrates that dead time does not affect the reduction of CMV in a noticeable way. Finally, both simulation and experimental results coincide with the theoretical analysis that the proposed SC-SPWM shows the best performance in reducing the CMV amplitude and changing frequency among these four SPWM methods, though it leads to a higher phase current distortion.

A novel adaptive switching method to reduce DC-Link capacitor ripple in PV based grid-connected inverter

In this paper, the developed switching method has been developed to generate trigger signals for the voltage source inverter (VSI) to reduce the current harmonics on the DC-link capacitor. In the novel switching method, at the durations where the DC link capacitor current is greatest, the waveform of the input current of the inverter and the waveform of the output current of the DC side are approximated. The main contribution is to provide a low harmonic content capacitor current with the same capacitor size, thereby increasing the power delivered to the grid.In order to examine the performance of the developed switching method, the spectrum of DC link current obtained by Fast Fourier Transform (FFT) in MATLAB/Simulink. Simulation results have been evaluated according to the value of the harmonic amplitude at the switching frequency. It shows novel switching strategy is more effective in reducing current ripples than the carrier-based Sinusoidal Pulse Width Modulation (SPWM) method which is used as a reference strategy.

A Modified Space Vector PWM Approach for Nine-Level Cascaded H-Bridge Inverter

This paper presents a modified space vector pulse width modulation (MSVPWM) technique for nine-level cascaded H-bridge (CHB) inverter. Based on a modular structure and absence of capacitor balancing problems, CHB inverter topology is preferred. Nowadays, space vector PWM (SVPWM) control scheme has achieved higher attention among different PWM techniques. In general, SVPWM method is realized based on disintegrating higher-level hexagons into a number of two-level hexagons. Compared to conventional SVPWM technique, the proposed MSVPWM technique reduces the computational burden and memory requirement involved in the realization of nine-level SVPWM. This is achieved by reducing the number of two-level hexagons without losing the inverter output voltage profile. Also a further modified space vector pulse width modulation technique is presented, which greatly reduces the computation efforts. The proposed SVPWM techniques are applied to a nine-level CHB inverter by using MATLAB/SIMULINK software tool and are compared with carrier-based sinusoidal pulse width modulation (SPWM) technique to validate the proposed techniques. The proposed SVPWM schemes produce lower harmonic distortion and higher DC bus utilization compared to SPWM technique. To verify the practicality of the proposed SVPWM techniques, experimental results are presented on nine-level CHB inverter.

Implementation and performance analysis of cascaded multilevel inverter using modified SVPWM techniques

The space vector pulse width modulation (SVPWM), which is considered as an efficient PWM technology can also be used for multilevel inverters. This method is originally designed for two-level inverters. This paper introduces a modified SVPWM technique. The cascaded H-bridge multilevel inverter (CMLI) of 7-level, 9-level and 11-level are simulated for three different carrier PWM techniques. Here, carrier-based sinusoidal pulse width modulation (SPWM), third harmonic injected pulse width modulation (THIPWM), and modified carrier-based SVPWM are used as modulation strategies. These modulation strategies include phase disposition technique (PD), phase opposition disposition technique (POD), Alternate Phase Opposition Disposition technique (APOD), and Phase Shifted Carrier (PSC). These strategies have been implemented by using simulation and validated by experiment. The detailed examination of the simulation results has been presented and validated with experimental results of 11-level CMLI.

Implementation and performance analysis of cascaded multilevel inverter using modified SVPWM techniques

The space vector pulse width modulation (SVPWM), which is considered as an efficient PWM technology can also be used for multilevel inverters. This method is originally designed for two-level inverters. This paper introduces a modified SVPWM technique. The cascaded H-bridge multilevel inverter (CMLI) of 7-level, 9-level and 11-level are simulated for three different carrier PWM techniques. Here, carrier-based sinusoidal pulse width modulation (SPWM), third harmonic injected pulse width modulation (THIPWM), and modified carrier-based SVPWM are used as modulation strategies. These modulation strategies include phase disposition technique (PD), phase opposition disposition technique (POD), Alternate Phase Opposition Disposition technique (APOD), and Phase Shifted Carrier (PSC). These strategies have been implemented by using simulation and validated by experiment. The detailed examination of the simulation results has been presented and validated with experimental results of 11-level CMLI.

Voltage Source Inverters Control using PWM/SVPWM For Adjustable Speed Drive Applications

Pulse Width Modulation variable speed drives are ncreasingly applied in many new industrial applications that require superior performance. Recently, developments in power electronics and semiconductor technology have lead improvements in power electronic systems. Hence, different circuit configurations namely multilevel inverters have become popular and considerable interest by researcher are given on them. Variable voltage and frequency supply to a.c drives is invariably obtained from a three-phase voltage source inverter. A number of Pulse width modulation (PWM) schemes are used to obtain variable voltage and frequency supply. The most widely used PWM schemes for three-phase voltage source inverters are carrier-based sinusoidal PWM and space vector PWM (SVPWM). There is an increasing trend of using space vector PWM (SVPWM) because of their easier digital realization and better dc bus utilization. This research focuses on step by step development SVPWM implemented on an Induction motor. The model of a three-phase a voltage source inverter is discussed based on space vector theory. Simulation results are obtained using MATLAB/Simulink environment for effectiveness of the study.

Analysis of Voltage Source Inverters using Space Vector PWM for Induction Motor Drive

The Adjustable Speed Drives (ADS) are generally used in industry. In most drives AC motors are applied. The standard drives used are Induction Motors (IM) and recently Permanent Magnet Synchronous Motors (PMSM) are also used. Developments in power electronics and semiconductor technology have lead to improvements in power electronic systems. Different circuit configurations namely multilevel inverters have become popular and considerable research interest is generated in them. Variable voltage and frequency supply to AC drives is invariably obtained from a three-phase voltage source inverter. A number of Pulse width modulation (PWM) schemes are used to obtain variable voltage and frequency supply. The most widely used PWM schemes for three-phase voltage source inverters are carrier-based sinusoidal PWM and space vector PWM (SVPWM). There is an increasing trend of using SVPWM because of their easier digital realization and better DC bus utilization. This paper proposes SVPWM implementation of an Induction motor. The model of a three-phase voltage source inverter is discussed based on space vector theory. Simulation results are obtained using MATLAB/Simulink environment.

Real-Time Calculation of Switching Angles Minimizing THD for Multilevel Inverters With Step Modulation

Multilevel inverters have been widely applied in industries. A family of optimal pulsewidth modulation (PWM) methods for multilevel inverters, such as step modulation, can generate output voltage with less harmonic distortion than popular modulation strategies, such as the carrier-based sinusoidal PWM or the space vector PWM. However, some drawbacks limit the application of optimal PWM. One of such crucial drawback is that the optimal switching angles could not be calculated in real-time and one has to rely on lookup tables with precalculated angles. We propose a novel real-time algorithm for calculating switching angles that minimizes total harmonic distortion (THD) for step modulation. We give a mathematical proof that the output voltage has the minimum THD. We implemented the algorithm on a digital signal processor and provide experimental results that verify the performance of the proposed algorithm.